삼성전자 서초사옥 모습 (사진=연합뉴스)

 

[Alpha Biz=(Chicago) Reporter Paul Lee] Samsung Electronics has made progress in commercializing 3-nano second-generation processes. It has been shown that the 3-nano second-generation process, which is scheduled to operate next year, can improve semiconductor performance by 20% compared to the existing 4-nano. Power efficiency and size have also improved, approaching the preoccupation of the next-generation semiconductor market.

Samsung Electronics will share the characteristics of the 3-nano process at the VLSI Symposium 2023, the world's most prestigious semiconductor society to be held in Japan in June. It is a venue to announce the "world's first 3-nano platform technology through a new MBCFET process" and plans to disclose information on the entire 3-nano second-generation process being developed by Samsung Electronics.

According to the pre-released data, the 3-nano second-generation process has improved in speed by 22% and power efficiency by 34% compared to the existing 4-nano process. The area (size) of semiconductors will be reduced by 21% compared to the past. The core competitiveness of semiconductors called 'performance (P), power (P), and size (A)' is all significantly improved. Miniaturization of semiconductor process is a process to maximize performance of PPA improvement.

This is the first time that Samsung Electronics has unveiled its next-generation process capabilities compared to its 4-nano process. So far, it has only been known to improve to 30% performance, 50% power, and 35% area compared to the 5-nano process.

 

[ⓒ AlphaBIZ. 무단전재-재배포 금지]