[Alpha Biz=(Chicago) Reporter Paul Lee] Samsung Electronics is going to develop '3D lamination' technology that stacks system semiconductor (logic) transistors vertically. 3D lamination is a technology that is attracting attention as a way to overcome semiconductor circuit refinement limitations and increase performance.

According to industries on the 25th, Samsung Electronics is in the process of R&D, which stacks the next-generation transistor structure 'GAA (Gate All Around)' vertically. Samsung Electronics DS Semiconductor Research Institute and Foundry Division are promoting related R&D together. It is believed that the 3D structure has been selected as the next generation GAA technology and has begun R&D for full-scale commercialization.

The 3D GAA structure currently being studied by Samsung Electronics is called '3DSFT'. It can be interpreted as expressing 3D and 3D stacking. The GAA, which is currently being mass-produced, is a two-dimensional (2D) structure that connects a single transistor to the side.

If the semiconductor process is refined, it will have problems due to interference between cells such as current leakage and difficulties in securing semiconductor areas. The way to overcome this limitation is to stack GAA transistors vertically. It minimizes cell interference and can accumulate many transistors in narrower spaces. It is like stacking NAND flash cells in a high level to increase performance.

3D GAA is meaningful in that it extends the 3D lamination structure, which has been used only in memory until now, to system semiconductors. Industry watchers say that as the existing FinFet structure faces limitations in the fine process below 3-nano, just as the paradigm changes to transistor structure with GAA, there is a transition to 3D GAA structure below 1-nano.

If Samsung Electronics, which has successfully mass-produced GAAs in advance, secures 3D GAAs first, chances are high that it will take the lead in competition for advanced semiconductor technologies.

 

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